1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which has a memory circuit section and a non-memory circuit section.
2. Description of the Related Art
Accompanying miniaturization of the LSI (Large Scale Integration), the functions of the LSI are made more advanced, the integration scale of the LSI is increased and the power consumption of the LSI is reduced. Due to particularly a smaller amount of signal charge caused by a lower power-supply voltage, however, a sensitivity exhibited by the LSI as a sensitivity to radiated light increases. It is thus feared that the probability of soft-error generation caused by radiated light dramatically increases.
Normally, soft-error generation caused by radiated light raises a problem that data stored in a storage device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is undesirably lost from the storage device when the radiated light hits the storage device. Stored data lost from a storage device is an accidental fault referred to an SEU (Single Event Upset).
In the event of a fault of this kind, the storage device itself is not damaged. Instead, data stored in a storage device is damaged and lost. The technical term ‘soft error’ is deliberately used in order to distinguish this soft error from a hard error which is attributed to a failure occurring in a device.
At the present day, in the case of a device whose reliability is important, an error avoidance technology at a circuit level is used as a countermeasure against an SEU. Examples of the device whose reliability is of importance are an LSI and a semiconductor circuit. A typical example of the error avoidance technology is an ECC (Error Checking and Correction) technology which makes use of an error detection code such as a parity bit.
As the operating voltage of a storage device becomes lower to accompany the progress in miniaturization of the storage device, the probability of the generation of a soft error increases. Thus, in the future, a countermeasure against the generation of a soft error is mandatory.
If an ECC circuit for encoding and decoding an error detection code such as a parity bit is added, however, the area of the LSI increases and an access speed is inevitably sacrificed due to comparisons which need to be made from time to time. In addition, generation of an SET (Single Event Transient) can no longer be ignored. The SET is a soft error generated in a logic circuit device which is other than the storage device cited above.
On top of that, unlike the storage device, in order to prevent an SET from occurring in a logic circuit device, it is impossible to have the logic circuit device designed to adopt an error avoidance technique based on an ECC circuit making use of parity bits or the like.
Thus, in order to prevent an SET from occurring in a logic circuit, there is no other choice than making the logic circuit redundant. In this case, a logic value output by an additional circuit required to make up the logic circuit must be compared from time to time with a logic value output by the original logic circuit.
In order to make the logic circuit redundant and compare a logic value output by an additional circuit required to make up the logic circuit with a logic value output by the original logic circuit from time to time, two to three original main logic circuits must be created. In addition, it is also necessary to prepare a circuit for the comparison purpose separately from the two to three original main logic circuits.
Thus, the area of the chip of the logic circuit device increases inevitably and the cost of manufacturing the chip also undesirably rises in a single burst. As a result, the power consumption becomes higher undesirably as well and the from-time-to-time comparisons also unavoidably deteriorate the performance of the logic circuit device.
For the reasons described above, if an LSI required to exhibit a high-reliability characteristic is provided with a technique of making the logic circuit redundant and comparing a logic value output by an additional circuit required to make up the logic circuit with a logic value output by the original logic circuit from time to time, the increased area of the chip of the LSI undesirably cancels aforementioned merits given by the miniaturization.
In addition, in the case of an LSI not much required to exhibit such a high-reliability characteristic, it is quite within the bounds of possibility that, as the miniaturization makes further progress, an unresolved problem caused by the further progress can no longer be tolerated in the applications of such an LSI. In such a case, the higher performance and the lower manufacturing cost which are results of the miniaturization of the LSI will be limited by a neck formed by the countermeasures against soft errors caused by radiated light.
As described above, a limit is imposed on the method for avoiding a soft error at the circuit level. Thus, in order to further reduce the manufacturing cost and the power consumption as a result of miniaturization, it is necessary to take a countermeasure for avoiding soft errors at the device level.
A SET countermeasure technology established by changing the pattern of a transistor is disclosed in documents such as Japanese Patent Laid-open No. 2007-073709.